The processor architecture is shown below; the CLP includes the following resources:
- Program execution and scheduling
- Data reporting
First of all, the CLP is dual-core. The CLP includes two identical processing cores on the same chip in order to boost performance. These 2 cores can be operated in different manners:
- They can be operated completely independently whereby each core executes its own program and does not know about the other.
- Or they can be operated in a synchronised manner whereby synchronisation triggers can be generated via the on-chip timing and synchronisation circuitry and whereby data can be exchanged via a dedicated on-chip RAM section (Intercom RAM).
There are no limitations in this respect. The dual-core architecture offers some additional flexibility and makes it e.g. possible to:
- Control 2 different motors from a single chip.
- Separate a control algorithm into various parts where the most intensive processing takes part on a dedicated core.
- Implement master/slave architectures.
Each core contains two full floating-point units that can be used in parallel. Floating point arithmetic will be according to a 32-bit format (IEEE-754 32 bit) with a 23 bit mantissa. This precision is generally found sufficient in the control world, and assures that the executing software is identical to the mathematical model.
Each core also fully supports fixed-point data types and arithmetic, and data can be exchanged between floating-point and fixed-point sections.
The executable program is stored internally (in on-chip SRAM., for gaining additional speed.
The on-chip SRAM is 1Mbit large, and enables to store a program of 30 KLOC. Experience has shown that control programs (with HBRISC technology) are quite small in size (typical size 4 KLOC), and there is thus plenty of margin in this respect.
CLP has further timing and synchronisation circuitry on board for the scheduling of SW execution. This scheduling is completely deterministic and is non-interruptible; and there is no operating system needed.