The CLP will be developed using the DARE (Designed Against Radiation Effects) technology (180 nm, 3.3 Volt) that has been developed and maintained by IMEC. It is a promising alternative as several ESA projects have already been led to propose a low-cost, ITAR-free silicon source based on a commercial foundry (UMC, United Microelectronics Corporation). It is today considered that this ASIC technology is the baseline for the CLP.
The CLP will be qualified according to ECSS-9000 level B and/or C flow.
Engineering models will also be made available for early developments.