Memory

CLP keeps its data normally in internal registers that are immediately available for processing.

The internal registers can be addressed directly and no data moves are required for processing (even if this capability remains possible). The CLP architecture is such that two operands can be processed with a single instruction without interrupting the program flow. The data path is thus optimal for high throughput applications and derived from the well known SHARC (Super Advanced Harvard Computer).

The number of internal registers is increased significantly when compared to HBRISC2(1024 per core). It has been observed in the past that a typical (and fairly complex) control model requires about 120 registers; this gives  a margin for growth with a factor of 8 in terms of complexity.

Additional memory is available in an on-chip SRAM that can also be addressed directly.  This makes it also possible to maintain long data sections (e.g. long tables) in the on-chip RAM section without slower external memory access.

CLP offers the user various manners to manage data:

  • In internal registers.
  • In on-chip SRAM.
  • In external memory.

To be noted is that, for accessing external  memory, the processor has error detection and correction circuitry on board (CRC unit and on-chip EDAC).

CLP contains an external memory I/F that will support various access protocols for external memory.

CLP also supports various methods for booting. The processor has an internal boot ROM for bringing it in an initial and well defined state. After that the user has various possibilities:

  • Boot further from one of its interfaces (load an externally supplied program in internal or external memory and start executing it).
  • Or load an executable program in  its internal memory and start executing from there.
  • Or load an external memory section and start executing from there.

Booting from an external interface is typically done in a laboratory environment where ones does not want to program EEPROM continuously. Booting from an EEPROM is typically done in the target -environment.

Boot times on CLP are short. For a typical control application, boot time is around 5 msec (for boot from an external EEPROM into internal SRAM with 20 KLOC of code and data).