The CLP program

The CLP program will follow a phased lifecycle as follows:

  • Phase 1 will be a specification phase, whereby the design of the processor will be fixed and will be validated via VHDL simulations. The specification of the development suite (software development environment or SDE) ¬†will also be established.
  • Phase 2 will be an implementation phase, whereby a CLP prototype will be implemented on an FPGA that will be submitted to functional test. This will be followed by the design, manufacturing and validation (functional, performance and radiation tests) of the CLP prototype with the DARE library (we will refer to this as the ASIC prototype). In the mean time, the SDE will be implemented and its validation will be initiated.
  • Phase 3 will be a qualification phase during which the CLP flight model will be manufactured and qualified, and during which the validation of the development suite will be finalised.

There will be 3 models of the processor:

  • A prototype on an FPGA;
  • An ASIC prototype;
  • The final flight model.

The evaluation board for the CLP technology will be based upon the FPGA prototype.

The program targets for the following deadlines:

  • A simulator that is representative for the processor will be available by the beginning of 2014.
  • The FPGA prototype, together with a beta version of the software development environment, will be available by the middle of 2015. The same applies to the evaluation board as this will be based upon the FPGA prototype.
  • The ASIC prototype will be available before the middle of 2016.